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IIJEE:Volume 5, Issue 2, February 2017

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Title:
Reconfigurable Test Architecture for Online Concurrent Fault Detection, Diagnosis and Repair
Author Name:
Mr. Chandra Singh Pachouri
Abstract:
ABSTRACT A complete and versatile online test solution based on reconfigurable test architecture is presented in the present paper. Reconfigurable test architecture works alongside the controllers for online concurrent fault detection. The output vectors of the controllers are concurrently monitored and any fault present is detected in a few cycles from the sensitization of the fault. The architecture is then reprogrammed to a similar set of diagnostic hardware to locate a sub block which is the cause for the fault. The same architecture is then reprogrammed to replace the faulty block thereby completing repair. The test architecture is designed based on configurable logic blocks. The design has several advantages viz. (i) it works well for critical VLSI controllers where shutting down or suspending the operation of a controller for testing is not possible and where the fault needs to be detected at the earliest, during the run time of the system, (ii) after a fault is detected, diagnosis can be performed online, (iii) once a faulty block is located, repair is also done online. Since fault detection, diagnosis and repair are completed online with one test hardware, the effective hardware overhead is negligible and the system can resume its function within a brief period. The applicability of the architecture is demonstrated for the control blocks in OC8051.
Cite this article:
Mr. Chandra Singh Pachouri , " Reconfigurable Test Architecture for Online Concurrent Fault Detection, Diagnosis and Repair" , IPASJ INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING (IIJEE) , Volume 5, Issue 2, February 2017 , pp. 031-035 , ISSN 2321-600X.
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