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IIJEE:Volume 5, Issue 8, August 2017

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Title:
AREA AND POWER EFFICIENT OF PIPELINE VLSI ARCHITECTURE OF THE 2-D DWT
Author Name:
Mr. V.L. Sinha
Abstract:
ABSTRACT Several techniques square measure accustomed scale back power dissipation by eliminating spurious transitions .Truncated multiplier factor is employed to scale back space and therefore the power dissipation of pipeline VLSI design of the second DWT and improve performance. The relationships that exist between the coefficients of the filters in varied sub bands may then be utilised to more enhance the in operation speed of the pipelines. In applications like video compression, medical imaging and geographic information analysis, its 2-D wave transforms that square measure used.
Cite this article:
Mr. V.L. Sinha , " AREA AND POWER EFFICIENT OF PIPELINE VLSI ARCHITECTURE OF THE 2-D DWT" , IPASJ INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING (IIJEE) , Volume 5, Issue 8, August 2017 , pp. 006-008 , ISSN 2321-600X.
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