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IIJEE:Volume 5, Issue 8, August 2017

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Title:
DESIGN OF A LOW POWER DOUBLE TAIL COMPARATOR USING GATED CLOCK AND POWER GATING TECHNIQUES
Author Name:
Mrs. Aradhya Sharma
Abstract:
ABSTRACT In this paper, performance of various types of dynamic double tail comparators (Gated clock and power gating technique) are compared in terms of their power, Delay, speed, Rise time, fall time, average time. The accuracy of comparators, which is defined by its power consumption and speed, is of keen interest in achieving overall higher performance of ADCs. In the domain of Signal processing with Low Power VLSI, the role of ADC system is essential. Many high speed ADCs, such as flash ADCs, require High speed, Low power comparators with small chip area. High-speed comparators suffer from low supply voltages especially when threshold voltage of the devices is not scaled at the same pace as the supply voltages of the modern CMOS process. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. . The maximum clock frequency of the proposed comparator can be 600GHz at supply voltages of 0.8 and 0.5 V, while consuming 111?w and 130 ?W, respectively.
Cite this article:
Mrs. Aradhya Sharma , " DESIGN OF A LOW POWER DOUBLE TAIL COMPARATOR USING GATED CLOCK AND POWER GATING TECHNIQUES" , IPASJ INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING (IIJEE) , Volume 5, Issue 8, August 2017 , pp. 009-010 , ISSN 2321-600X.
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