IPASJ INTERNATIONAL JOURNAL OF ELECTRONICS & COMMUNICATION (IIJEC)

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Block Level Design Implementation of 100 Mbps Ethernet Telemetry using Vivado TEMAC IP core in Artix-7 , Authors : Gowri J , Manoj G, Karunakara P Menon,IPASJ INTERNATIONAL JOURNAL OF ELECTRONICS & COMMUNICATION (IIJEC) ,http://www.ipasj.org/IIJEC/IIJEC.htm

Volume & Issue no: Volume 7, Issue 4, April 2019


Title:
Block Level Design Implementation of 100 Mbps Ethernet Telemetry using Vivado TEMAC IP core in Artix-7
Author Name:
Gowri J , Manoj G, Karunakara P Menon
Abstract:
ABSTRACT Telemetry is used to acquire data from a remote location and transfer to a location where it is analyzed. In sonar systems, data acquired is transmitted and received at desired location using Ethernet. Here the Ethernet data coming from a location is received and it is transmitted to another location as needed. Designs in which IPs are added as RTL source files are a little complex for the modern IP which has complex interfaces and port mappings. Block level design of the receiver- transmitter system is implemented using Vivado IPs integrator tool and is implemented on ARTIX 7 FPGA evaluation board. Vivado IP integrator tool integrates the complex IPs in a single step. Keywords: Ethernet, FPGA, UDP, Vivado, IP
Cite this article:
Gowri J , Manoj G, Karunakara P Menon , " Block Level Design Implementation of 100 Mbps Ethernet Telemetry using Vivado TEMAC IP core in Artix-7 " , IPASJ INTERNATIONAL JOURNAL OF ELECTRONICS & COMMUNICATION (IIJEC), Volume 7, Issue 4, April 2019 , pp. 001-007 , ISSN 2321-5984.
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